----------------------------------------------------------------------
-- Top, Clock skew
-- James Carroll
-- BYU ECEn 620, October 2008
----------------------------------------------------------------------
Library ieee;
	use ieee.std_logic_1164.all;
	use ieee.numeric_std.all;
	
entity clock_skew is
	generic(
        -- Units here are ns
        -- Assumptions:
        --   1. Tsr >= Tpr
        --   2. Tsl >= Tpl
        --   3. Tpi, Tpr, Tpl >= 0
        -- Note: delta may be less than or greater than zero
		Tpt:integer:=8;     -- combinational logic propagation delay
		Tst:integer:=8;     -- combinational settling delay
		Tsr:integer:=8;     -- register settling delay
		Tpr:integer:=8;     -- register propagation delay
		Tck:integer:=8;     -- clock period (ns)
		Tpi:integer:=8;     -- interconnect propagation delay
        delta:integer:=8    -- skew (see below)
        -- t1 = output of combinational logic (CL1) begins to load
        -- in register (R1).
        -- t2 = CL2 begins to load in R2.
        -- Delay between these two is skew
        -- t2 = t1 + delta
        -- delta = t2 - t1
	);
end entity;

architecture clock_skew of clock_skew is

    signal R1, R2, R1in, C1, C1in, C1out : std_logic_vector(1 downto 0);
begin

    process(clk)
    begin
        if clk'event and clk='1' then --just use "clk='1'" for single-phase model
        R1 <= R1in;
        R2 <= transport C1out after delta;
        end if;
    end process;

    R1out(0) <= transport R1(0) after tpr;
    R1out(1) <= transport R1(1) after tsr;
    C1in <= transport R1out after tpi;
    C1 = C1in + 1;
    C1out(0) <= transport C1(0) after tpl;
    C1out(1) <= transport C1(1) after tsl; 
end architecture;
